ST7285C datasheet(23/117 Pages) STMICROELECTRONICS

部件名	ST7285C

功能描述	8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES

PDF	117 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

标志

23 / 117 page

23/117

ST7285C

POWER SAVING MODES (Cont’d)

3.6.3 Halt Mode

The HALT instruction places the MCU in its lowest

power consumption mode. In HALT mode the in-

ternal oscillator is turned off, causing all internal

processing to be halted. During HALT mode, the I

bit in the CC Register is cleared so as to enable

External Interrupts.

All other registers and memory remain unaltered

and all Input/Output lines remain unchanged. This

state will endure until an External Interrupt (I1, I2,

I9, I10) or a Reset is generated, whereupon the in-

ternal oscillator is restarted. A delay of 4096 CPU

clock cycles is initiated prior to restarting the appli-

cation, in order to allow the oscillator to stabilize.

The External Interrupt or Reset causes the Pro-

gram Counter to be set to the address of the corre-

sponding Interrupt or Reset Service Routine.

Figure 12. Halt Mode Flow Chart

VR02062E

EXTERNAL

INTERRUPT

WAIT

HALT

STOP OSCILLATOR

AND ALL CLOCKS

CLEAR I-BIT

RESET

OSCILLATOR

IN SLOW MODE

TURN ON

OSCILLATOR

WAIT FOR 4096 CPU

CLOCK TIME DELAY

FETCH RESET

VECTOR OR

SERVICE INTERRUPT

ST7285C 数据表(PDF) 23 Page - STMicroelectronics

ST7285C 数据表(HTML) 23 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载