ST9291 datasheet(11/20 Pages) STMICROELECTRONICS

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R239 (EFh)

SYS. STACK POINTER LOW

R238 (EEh)

SYS. STACK POINTER HIGH

R237 (EDh)

USER STACK POINTER LOW

R236 (ECh)

USER STACK POINTER HIGH

R235 (EBh)

MODE REGISTER

R234 (EAh)

PAGE POINTER

R233 (E9h)

R232 (E8h)

R231 (E7h)

FLAGS

R230 (E6h)

CENTRAL INT. CNTL REG

R229 (E5h)

PORT5

R228 (E4h)

PORT4

R227 (E3h)

PORT3

R226 (E2h)

PORT2

R225 (E1h)

PORT1

R224 (E0h)

PORT0

Figure 1-8. System Register

1.1.3 SYSTEM REGISTERS

Following is the description of System Registers.

For PORT0 to PORT5 Registers, please refer to

I/O Port Chapter.

1.1.3.1 Central Interrupt Control Register

This Register CICR is located in the system Regis-

ter Group at the address R230 (E6h). Please refer

to “INTERRUPT” and “DMA” chapters in order to

get the background of the ST9 interrupt philoso-

phy.

CICR R230 (E6h) System Read/Write

Central Interrupt Control Register

Reset Value : 1000 0111

GCEN TLIP TLI

IEN

IAM CPL2 CPL1 CPL0

b7 = GCEN:

Global Counter Enable. This bit is the

Global Counter Enable of the Multifunction Timers.

The GCEN bit is ANDed with the CE (Counter En-

able) bit of the Timer Control Register (explained in

the Timer chapter) in order to enable the Timers

when both bits are set. This bit is set after the Re-

set cycle.

b6 = TLIP:

Top Level Interrupt Pending. This bit is

automatically set when a Top Level Interrupt Re-

quest is recognized. This bit can also be set by

Software in order to simulate a Top Level Interrupt

Request.

b5 = TLI:

Top Level Interrrupt bit. When this bit is

set, a Top Level interrupt request is acknowledged

depending on the IEN bit and the TLNM bit (in

Nested Interrupt Control Register). If the TLM bit is

reset the top level interrupt acknowledgement de-

pends on the TLNM alone.

b4 = IEN:

Enable Interrupt. This bit, (when set), al-

lows interrupts to be accepted. When reset no in-

terrupts other than the NMI can be acknowledged.

It is cleared by interrupt acknowledgement for con-

current mode and set by interrupt return (iret). It

can be managed by hardware and software (ei

and di instruction).

b3 = IAM:

Interrupt Arbitration Mode. This bit cov-

ers the selection of the two arbitration modes, the

Concurrent Mode being indicated by the value “0”

and the Fully Automatic Nested Mode by the value

“1”. This bit is under software control.

b2-b0 = CPL2-CPL0:

Current Priority Level. These

three bits record the priority level of the interrupt

presently under service (i.e. the Current Priority

Level, CPL). For these priority levels 000 is the

highest priority and 111 is the lowest priority. The

CPL bits can be set by hardware or software and

give the reference by which following interrupts are

either left pending or able to interrupt the current

interrupt. When the present interrupt is replaced by

one of a greater priority, the current priority value is

automatically stored until required.

ST9291

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