AI00822D

11 0

An A0

Qn

Q0

DATA OUT

D

S

Q

READ

S

WRITE

ADDR

OP

CODE

10

An

DATA IN

D

Q

Dn

D0

X

BUSY

READY

S

ERASE

WRITE

ENABLE

1

0

Xn X0

D

OP

CODE

1

01

S

ERASE

WRITE

DISABLE

1

0

Xn X0

D

OP

CODE

00

0

CHECK

STATUS

XX

A0

1X

ADDR

OP

CODE

Figure 6. READ, WRITE, EWEN, EWDS Sequences

If the ST93C06 is still performing the erase cycle,

the Busy signal (Q = 0) will be returned if S is driven

high, and the ST93C06 will ignore any data on the

bus. When the erase cycle is completed, the Ready

signal (Q = 1) will indicate (if S is driven high) that

the ST93C06 is ready to receive a new instruction.

Write

The Write instruction (WRITE) is followed by the

address and the 8 or 16 data bits to be written. Data

input is sampled on the Low to High transition of

the clock. After the last data bit has been sampled,

Chip Select (S) must be brought Low before the

next rising edge of the clock (C) in order to start the

self-timed programming cycle. If the ST93C06 is

still performing the write cycle, the Busy signal (Q

= 0) will be returned if S is driven high, and the

ST93C06 will ignore any data on the bus. When the

write cycle is completed, the Ready signal (Q = 1)

will indicate (if S is driven high) that the ST93C06

is ready to receive a new instruction. Programming

is internally self-timed (the external clock signal on

C input may be disconnected or left running after

the start of a programming cycle) and does not

require an Erase instruction prior to the Write in-

struction (The Write instruction includes an auto-

matic erase cycle before programing data).

Notes: 1. An: n = 3 for x16 org. and 4 for x8 org.

2. Xn: n = 3 for x16 org. and 4 for x8 org.

7/15

ST93C06, ST93C06C