AI01438

C

C

MSB

LSB

CPHA

D or Q

0

1

CPOL

0

1

Figure 3. Data and Clock Timing

AI01439

SPI Interface with

(CPOL, CPHA) =

('0', '0') or ('1', '1')

MICROCONTROLLER

(ST6, ST7, ST9)

ST95xx0

SCK

SDI

SDO

C

Q

D

Figure 4. Microcontroller and SPI Interface Set-up

Hold (HOLD). The HOLD pin is used to pause

serial communications with a ST95022 without re-

setting the serial sequence. To take the Hold con-

dition into account, the product must be selected

(S = 0). Then the Hold state is validated by a high

to low transition on HOLD when C is low. To resume

the communications, HOLD is brought high while

C is low. During the Hold condition D, Q, and C are

at a high impedance state.

When the ST95022 is under the Hold condition, it

is possible to deselect the device. However, the

serial communications will remain paused after a

reselect, and the chip will be reset.

The ST95022 can be driven by a microcontroller

with its SPI peripheral running in either of the two

following modes: (CPOL, CPHA) = (’0’, ’0’) or

(CPOL, CPHA) = (’1’, ’1’).

For these two modes, input data is latched in by the

low to high transition of clock C, and output data is

available from the high to low transition of Clock

(C).

The difference between (CPOL, CPHA) = (0, 0) and

(CPOL, CPHA) = (1, 1) is the stand-by polarity: C

remains at ’0’ for (CPOL, CPHA) = (0, 0) and C

remains at ’1’ for (CPOL, CPHA) = (1, 1) when there

is no data transfer.

3/16

ST95022