STA013 datasheet(15/38 Pages) STMICROELECTRONICS

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DATA_REQ_ENABLE

Address: 0x18

Type: R/W

Software Reset: 0x00

Hardware Reset: 0x00

MSB

LSB

Description

buffered output clock

request signal

MUTE

Address: 0x14

Type: R/W

Software Reset: 0x00

Hardware Reset: 0x00

MSB

LSB

XXXXX

X = don’t care; 0 = normal operation; 1 = mute

The MUTE command is handled according to the

state of the decoder, as described in section 2.5.

MUTE sets the clock running.

CMD_INTERRUPT

Address: 0x16

Type: R/W

Software Reset: 0x00

Hardware Reset: 0x00

MSB

LSB

XXX

XXXX

X = don’t care;

0 = normal operation;

1 = write into I

2C/Ancillary Data

The INTERRUPT is used to give STA013 the

command to write into the I2C/Ancillary Data

Buffer (Registers: 0x59 ... 0x5D). Every time the

Master has to extract the new buffer content (5

bytes) it writes into this register, setting it to a

non-zero value.

SYNCSTATUS

Address: 0x40

Type: RO

Software Reset: 0x00

Hardware Reset: 0x00

MSB

LSB

Description

XXXX

SS1

SS0

Research of sync word

Wait for Confirmation

Synchronised

not used

The DATA_REQ_ENABLE register is used to

configure Pin n. 28 working as buffered output

clock or data request signal, used for multimedia

mode.

The buffered Output Clock has the same fre-

quency than the input clock (XTI)

STA013 - STA013B - STA013T

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