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数据搜索系统，热门电子元器件搜索 |
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STA013 数据表(PDF) 23 Page - STMicroelectronics |
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STA013 数据表(HTML) 23 Page - STMicroelectronics |
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23 / 38 page  PLLFRAC_L ([7:0]) MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 PLLFRAC_H ([15:8]) MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 PF15 PF14 PF13 PF12 PF11 PF10 PF9 PF8 Address: 0x64 - 0x65 Type: R/W Software Reset: 0x46 | 0x5B Hardware Reset: 0xNA | 0x5B The registers are considered logically concate- nated and contain the fractional values for the PLL, used to select the internal configuration. After Reset, the values are NA, and the opera- tional setting are done when the MPEG synchro- nisation is achieved. The following formula describes the relationships among all the STA013 fractional PLL parameters: OCLK_Freq = 1 X + 1 ⋅ MCLK_freq N + 1 ⋅ M + 1 + FRAC 65536 where: FRAC=256 x FRAC_H + FRAC_L (decimal) These registers are a reference for 48 / 24 / 12 / 32 / 16 / 8KHz audio. FRAME_CNT_L MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 FC7 FC6 FC5 FC4 FC3 FC2 FC1 FC0 FRAME_CNT_M MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 FC15 FC14 FC13 FC12 FC11 FC10 FC9 FC8 FRAME_CNT_H MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 FC23 FC22 FC21 FC20 FC19 FC18 FC17 FC016 Address: 0x67, 0x68, 0x69 Type: RO Software Reset: 0x00 Hardware Reset: 0x00 The three registers are considered logically con- catenated and compose the Global Frame Counter as described in the table. It is updated at every decoded MPEG Frame. The registers are reset on both hardware and software reset. AVERAGE_BITRATE Address: 0x6A Type: RO Software Reset: 0x00 Hardware Reset: 0x00 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 AB7 AB6 AB5 AB4 AB3 AB2 AB1 AB0 AVERAGE_BITRATE is a read-only register and it contains the average bitrate of the incoming bit- stream. The value is rounded with an accuracy of 1 Kbit/sec. SOFTVERSION Address: 0x71 Type: RO MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 SV7 SV6 SV5 SV4 SV3 SV2 SV1 SV0 After the STA013 boot, this register contains the version code of the embedded software. STA013 - STA013B - STA013T 23/38 |
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