5 - POWER SUPPLIES

5.1 - Supplies

The chip operates from a power supply of 3.0 to

5.5 Volts. All interface circuits to the baseband

chips are operated between these supplies.

Six on-chip regulators are included on-chip which

provide to all parts of the circuit separate regulated

voltage supplies of -2.85

±0.15 Volts relative to the

top rail for the RF circuitry, the IF circuitry, the digital

circuitry and for the three VCO’s.

The chip can be operated in 3 modes, power down,

receive and transmit. Power down is activated tak-

The built-in regulators can be by-passed ,if so

required.

5.2 - Ground Plane Connections

The chip has been designed to be decoupled to the

strongly recommended that the chip be mounted

Because the base band chip is specified relative to

a negative ground, it is further recommended that

the board used is a 4 layer board with both a

has the additional advantage of providing good

high frequency decoupling between supplies.

depe nds on which external equipment is con-

nected. For testing the baseband section, this is

product, this will depend on the application.

For clarity all voltages specified in this document

supply is varied.

6 - ELECTRICAL CHARACTERISTICS

Symbol

Parameter

Min.

Typ.

Max.

Unit

Power Supply Voltage (unregulated)

-3

-5.5

V

Power Supply bypassing Internal Regulators (this is also interface supply)

-2.7

-3

V

IRX

Receive Mode

32

40

mA

ITX

Transmit Mode

68

80

mA

IQ

Standby/Power Down

20

µA

7 - TIMING INFORMATION

7.1 - Turn on-off Times

Times are relative to the NTXEN transition (high to low for receive to transmit and low to high for transmit

to receive).

Symbol

Parameter

Min.

Typ.

Max.

Unit

Turn-on Time From standby to receive

10

µs

PA Power Ramp up to reach -3dB of final power

27.78

µs

Switchover Time Transmit to Receive (LNA/first mixer active)

27.78

µs

7.2 - Channel Select Timing

PRGCLK must be high before NPRGEN goes low to programme the synthesizer.

Figure 2 : Timing of Serial Programming Data

NPRGEN

PRGCLK

PRGD

PROGRAM

CODE

Orde r of NPRGEN &PRGD unimportant

Code cha nge s on Rising Edge of NPRGEN

Note that although a new program code is implemented on the rising edge of the NPRGEN, the transmitted

power level is delayed until at the start of the next burst of transmission. In order to change transmit power

during a conversation, the required power code must be serially loaded with the power change instruction.

STB4395

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