8 - TRANSCEIVER SECTION (continued)

8.4 - System Clock Input

Symbol

Description

Min.

Typ.

Max.

Unit

Reference Frequency

14.4

MHz

0.4

0.8

V

-40

µA

µA

(*1) limits according to ETSI specification

8.5 - RF/NRF Receive/Transmit Pins

Symbol

Description

Min.

Typ.

Max.

Unit

Input Impedance (balanced, RX)

300

Ω // 3.5pF

-

VSWR

VSWR

1.5:1

-

DC Input Voltage

0V

AC Input Power

0

dBm

Output Impedance (balanced, TX)

300

Ω // 3pF

-

8.6 - Digital Input Buffers NTXEN, PRGD, NPRGEN, PRGCLK, FN

Symbol

Description

Min.

Typ.

Max.

Unit

Upper Level Input Voltage

V

Lower Level Input Voltage

V

Input Current High

-10

µA

Input Current Low

40

µA

Tt

Input Edge Transition

0.1

1

µs/V

8.7 - Digital Output Buffers xLOCK, DO

Symbol

Description

Min.

Typ.

Max.

Unit

Upper Level Output Voltage

V

Lower Level Output Voltage

V

Rise Time (load of 5pF)

0.3

µs/V

Fall Time (load of 5pF)

0.4

µs/V

8.8 - Receiver - FSH Tri State Input

Symbol

Description

Min.

Typ.

Max.

Units

Upper Level Input Voltage

V

Lower Level Input Voltage

V

Tri State Current

-10

10

µA

Input Current High

-100

µA

Input Current Low

100

µA

Input Edge Transition

0.1

1

µs/V

STB4395

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