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M95010-RBN6TG/W 数据表(PDF) 13 Page - STMicroelectronics

部件名 M95010-RBN6TG/W
功能描述  4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock
PDF  37 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

M95010-RBN6TG/W 数据表(HTML) 13 Page - STMicroelectronics

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M95040, M95020, M95010
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set pri-
or to each WRITE and WRSR instruction. The only
way to do this is to send a Write Enable instruction
to the device.
As shown in Figure 8., to send this instruction to
the device, Chip Select (S) is driven Low, and the
bits of the instruction byte are shifted in, on Serial
Data Input (D). The device then enters a wait
state. It waits for a the device to be deselected, by
Chip Select (S) being driven High.
Figure 8. Write Enable (WREN) Sequence
Write Disable (WRDI)
One way of resetting the Write Enable Latch
(WEL) bit is to send a Write Disable instruction to
the device.
As shown in Figure 9., to send this instruction to
the device, Chip Select (S) is driven Low, and the
bits of the instruction byte are shifted in, on Serial
Data Input (D).
The device then enters a wait state. It waits for a
the device to be deselected, by Chip Select (S) be-
ing driven High.
The Write Enable Latch (WEL) bit, in fact, be-
comes reset by any of the following events:
–Power-up
WRDI instruction execution
WRSR instruction completion
WRITE instruction completion
Write Protect (W) line being held Low.
Figure 9. Write Disable (WRDI) Sequence
C
D
AI01441D
S
Q
2
1
34567
High Impedance
0
Instruction
C
D
AI03790D
S
Q
2
1
34567
High Impedance
0
Instruction



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