Clock Inputs

CLK

CLK

ADS5463/5444/5440

~2.4V

AVDD5

Internal

Clock

Buffer

1000 W

Parasitic

~0.8pF

GND

~0.5pF

package

~2.5nHBondWire

~200fF

bondpad

GND

package

bondpad

GND

AVDD5

~2.5nHBondWire

~0.5pF

~200fF

1000 W

Parasitic

~0.8pF

CLK

ADS5463

CLK

SquareWaveor

SineWave

0.01 F

m

0.01 F

m

S0168-05

ADS5463

The ADS5463 clock input can be driven with either a differential clock signal or a single-ended clock input. The

equivalent clock input circuit can be seen in Figure 38. In low-input-frequency applications, where jitter may not

be a big concern, the use of a single-ended clock (as shown in Figure 39) could save cost and board space

without much performance tradeoff. When clocked with this configuration, it is best to connect CLK to ground

with a 0.01-

µF capacitor, while CLK is ac-coupled with a 0.01-µF capacitor to the clock source, as shown in

Figure 39.

Figure 38. Clock Input Circuit

Figure 39. Single-Ended Clock

Copyright © 2006–2008, Texas Instruments Incorporated

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