AD8260ACPZ-R7 datasheet(5/32 Pages) AD

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AD8260

Rev. 0 | Page 5 of 32

Parameter

Conditions

Min

Typ

Max

Unit

ACCURACY

Absolute Gain Error

All gain codes, limits are 3σ

−0.5

±0.15

+0.5

Gain Law Conformance (DNL)

Differential gain error code-to-code

−0.3

±0.15

+0.3

GAIN CONTROL

Gain Step per Code

3.0

Gain Range

Default = −6dB to +24 dB

Response Time

30 dB gain change (gain code stepped from 0001 to 1011)

LOGIC INTERFACES

High Level Input Voltage

1.4

Low Level Input Voltage

0.8

Logic Input Bias Current

Logic high, VLOGIC = 3.3 V

0.2

μA

Logic low

POWER SUPPLY

Supply Voltage

Single supply

3.3

Dual supply

±3.3

±5

Quiescent Current

Full chip enabled (TXEN = 1, ENBL = 1, gain code = 0001)

28.3

TXEN = 0, ENBL = 1, gain code = 0001, driver off, DGA on

19.1

TXEN = 1, ENBL = 1, gain code = 0000, driver on, DGA off

10.8

Chip disabled (TXEN = 0, ENBL = 0, gain code = 0000)

μA

VS = ±5 V, no signal

34.2

PSRR

Max gain (gain code = 1011), gain = 24 dB, 1 MHz

−30

Driver amplifier, 1 MHz

−48

Power Dissipation

No signal

No signal, VPOS − VNEG = 10 V

342

ENABLE TIMES

Chip Enable Time

Bias only, TXEN = 0, gain code = 0000, ENBL = 0 to 1

0.4

μs

All at once, TXEN = 0 to 1, gain code = 0000 to 0001,

ENBL = 0 to 1

0.3

μs

Preamplifier and DGA Enable Time

ENBL = 1, TXEN = 0, gain code = 0000 to 0001

0.3

μs

Driver Enable Time

ENBL = 1, gain code = 0001, TXEN stepped from 0 to 1

0.2

μs

DISABLE TIMES

Chip Disable Time

TXEN = 1 to 0, gain code = 0001 to 0000,

ENBL = 1 to 0, ISUPPLY = 100 μA

μs

All at once, TXEN = 1 to 0, gain code = 0001 to 0000,

ENBL = 1 to 0, ISUPPLY = 35 μA

μs

Preamplifier and DGA Disable Time

ENBL = 1, TXEN = 0, gain code = 0001 to 0000

0.4

μs

Driver Disable Time

ENBL = 1, gain code = 0000, TXEN = 1 to 0

2.2

μs

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