SSM2604CPZ-R2 datasheet(12/28 Pages) AD

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SSM2604

Rev. 0 | Page 12 of 28

ANALOG INTERFACE

Signal Chain

The SSM2604 includes stereo single-ended line inputs to the

on-board ADC. In addition, the line inputs can be routed and

mixed directly to the output terminals via the BYPASS bit

(Register R4, Bit D3). The SSM2604 also includes line outputs

from the on-board DAC.

Stereo Line Inputs

The SSM2604 contains a set of single-ended stereo line inputs

(RLINEIN and LLINEIN) that are internally biased to VMID

by way of a voltage divider between AVDD and AGND. The

line input signal can be connected to the internal ADC and, if

desired, routed directly to the outputs via the bypass path by

using the BYPASS bit (Register R4, Bit D3).

ADC

BYPASS

LINEIN

AVDD

VMID

AGND

–

Figure 17. Line Input to ADC

The line input volume can be adjusted from −34.5 dB to +33 dB

in steps of +1.5 dB by setting the LINVOL (Register R0, Bit D0

to Bit D5) and RINVOL (Register R1, Bit D0 to Bit D5) bits.

Volume control, by default, is independently adjustable on

both right and left line inputs. However, the LRINBOTH or

RLINBOTH bit, if selected, simultaneously loads both sets of

volume control with the same value. The user can also set the

LINMUTE (Register R0, Bit D7) and RINMUTE (Register R1,

Bit D7) bits to mute the line input signal to the ADC.

Note that when sourcing audio data from line inputs, the maxi-

mum full-scale input of the ADC is 1.0 V rms when AVDD = 3.3 V.

Do not source any input voltage larger than full scale to avoid

overloading the ADC, which causes distortion of sound and

deterioration of audio quality. For best sound quality in line

inputs, gain should be carefully configured so that the ADC

receives a signal equal to its full scale. This maximizes the

signal-to-noise ratio for best total audio quality.

Bypass Path to Output

The line inputs can be routed and mixed directly to the output

terminals via the BYPASS (Register R4, Bit D3) software control

the output terminals and is not digitally converted. The bypass

signal at the output mixer is the same level as the output of the

PGA associated with each line input.

Line Outputs

The DAC outputs and the line inputs (the bypass path) are

summed at an output mixer.

LINE OUTPUT

AVDD

VMID

AGND

BYPASS

DACSEL

LINE

INPUT

DAC

OUTPUT

Figure 18. Output Signal Chain

The maximum output level of the line outputs is 1.0 V rms

when AVDD and HPVDD = 3.3 V. To suppress audible pops

and clicks, the line outputs are held at the VMID dc voltage

level when the device is set to standby mode.

The stereo line outputs of the SSM2604, the LOUT and

ROUT pins, are able to drive a load impedance of 10 kΩ and

50 pF. The line output signal levels are not adjustable at the

output mixer, having a fixed gain of 0 dB.

DIGITAL AUDIO INTERFACE

The digital audio input can support the following four

digital audio communication protocols: right-justified mode,

left-justified mode, I2S mode, and digital signal processor

(DSP) mode.

The mode selection is performed by writing to the FORMAT

bits of the digital audio interface register (Register R7, Bit D1

and Bit D0). All modes are MSB first and operate with data of

16 to 32 bits.

Recording Mode

On the RECDAT output pin, the digital audio interface can

send digital audio data for recording mode operation. The

digital audio interface outputs the processed internal ADC

digital filter data onto the RECDAT output. The digital audio

data stream on RECDAT comprises left- and right-channel

audio data that is time domain multiplexed.

The RECLRC is the digital audio frame clock signal that

separates left- and right-channel data on the RECDAT lines.

The BCLK signal acts as the digital audio clock. Depending on

if the SSM2604 is in master or slave mode, the BCLK signal is

either an input or an output signal. During a recording opera-

tion, RECDAT and RECLRC must be synchronous to the BCLK

signal to avoid data corruption.

Playback Mode

On the PBDAT input pin, the digital audio interface can receive

digital audio data for playback mode operation. The digital audio

data stream on PBDAT comprises left- and right-channel audio

data that is time domain multiplexed. The PBLRC is the digital

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