SSM2604

Rev. 0 | Page 16 of 28

TYPICAL APPLICATION CIRCUITS

AVDD VMID AGND

DVDD DGND

ROUT

DIGITAL

PROCESSOR

RLINEIN

ADC

LLINEIN

ADC

DAC

DAC

LOUT

OSC

CLK GEN

MCLK/XTI

XTO

CLKOUT

CONTROL INTERFACE

SDIN

SCLK

DIGITAL AUDIO INTERFACE

PBDAT RECDAT BCLK PBLRC RECLRC

DAC

ADC

PWROFF

REF

LINE

OSC

CLKOUT

BYPASS

SSM2604

BYPASS

Figure 26. Power Management Functional Location Diagram (Control Register R6, Bit D0 to Bit D7)

CONNECTION UNDER CHIP

DACLRC

DACDAT

SCLK

ADCDAT

ADCLRC

BCLK

SDIN

R-LINE INPUT

L-LINE INPUT

+3.3V_VA

+3,3V_VD

C11

0.1uF

J1

BNC

1

C13

1uF

R4

NC

R8

100

C14

1uF

+

C12

4.7uF

B1

FB

C8

220PF

L1

47uH,15mA

C9

22pF

C5

1uF

C3

0.1uF

J2

BNC

1

C7

1uF

R5

47K

R1

5.6K

U1

SSM2604

17

16

8

7

9

10

6

20

18

19

1

2

12

11

5

15

LLINEIN

RLINEIN

PBLRC

PBDAT

RECDAT

RECLRC

BCLK

NC

SDIN

SCLK

MCLK/XTI

XTO

ROUT

LOUT

CLKOUT

VMID

+

C1

10uF

C6

220PF

R7

100

R6

47K

C10

22pF

C2

0.1uF

Y1

12.288MHz

R3

5.6K

+ C4

10uF

I2S[0..4]

I2C[0..1]

R2

NC

10M

NC

10M

NC

Figure 27. Typical Application Circuit