ADE5569 datasheet(67/148 Pages) AD

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Preliminary Technical Data

ADE5166/ADE5169/ADE5566/ADE5569

Rev. PrB | Page 67 of 148

VAR*

*AVAILABLE ONLY IN THE ADE5569 AND ADE5169.

CFxSEL[1:0]

WATT

VARMSCFCON

MODE2 REGISTER 0x0C

Irms

CFx PULSE

OUTPUT

CFxNUM

CFxDEN

DFC

Figure 57. Energy-to-Frequency Conversion

Two digital-to-frequency converters (DFC) are used to generate

the pulsed outputs. When WDIV = 0 or 1, the DFC generates a

pulse each time 1 LSB in the energy register is accumulated. An

output pulse is generated when a CFxNUM/CFxDEN number

of pulses are generated at the DFC output. Under steady load

conditions, the output frequency is proportional to the active

power, reactive power, apparent power, or Irms, depending on

the CFxSEL bits in the MODE2 register (0x0C).

Both pulse outputs can be enabled or disabled by clearing or

setting Bit DISCF1 and Bit DISCF2 in the MODE1 register

(0x0B), respectively.

Both pulse outputs set separate flags in the Interrupt Status 2 SFR

(MIRQSTM, 0xDD), CF1 and CF2. If the CF1 and CF2 enable

bits in the Interrupt Enable 2 SFR (MIRQENM, 0xDA) are set,

the 8052 core has a pending ADE interrupt. The ADE interrupt

stays active until the CF1 or CF2 status bits are cleared (see the

Energy Measurement Interrupts section).

Pulse Output Configuration

The two pulse output circuits have separate configuration bits

in the MODE2 Register (0x0C). Setting the CFxSEL bits to

0b00, 0b01, or 0b1x configures the DFC to create a pulse output

proportional to active power, to reactive power (not available in

the ADE5566 and ADE5166), or to apparent power or Irms,

respectively.

The selection between Irms and apparent power is done by the

VARMSCFCON bit in the MODE2 register (0x0C). With this

selection, CF2 cannot be proportional to apparent power if CF1

is proportional to Irms, and CF1 cannot be proportional to

apparent power if CF2 is proportional to Irms.

Pulse Output Characteristic

The pulse output for both DFCs stays low for 90 ms if the pulse

period is longer than 180 ms (5.56 Hz). If the pulse period is

shorter than 180 ms, the duty cycle of the pulse output is 50%.

The pulse output is active low and should preferably be

connected to an LED, as shown in Figure 58.

VDD

Figure 58. CF Pulse Output

The maximum output frequency with ac input signals at

full scale and CFxNUM = 0x00 and CFxDEN = 0x00 is

approximately 21.1 kHz.

The ADE5166/ADE5169/ADE5566/ADE5569 incorporate two

registers per DFC, CFxNUM[15:0] and CFxDEN[15:0], to set

the CFx frequency. These are unsigned 16-bit registers that can

be used to adjust the CFx frequency to a wide range of values.

These frequency scaling registers are 16-bit registers that can

scale the output frequency by 1/216 to 1 with a step of 1/216.

If 0 is written to any of these registers, 1 is applied to the

ensure proper operation. If the ratio of the CFxNUM/CFxDEN

registers is greater than 1, the register values are adjusted to a

ratio of 1. For example, if the output frequency is 1.562 kHz

while the content of CFxDEN is 0 (0x000), the output frequency

can be set to 6.1 Hz by writing 0xFF to the CFxDEN register.

ENERGY REGISTER SCALING

The ADE5166/ADE5169/ADE5566/ADE5569 provide measure-

ments of active, reactive, and apparent energies that use separate

paths and filtering for calculation. The difference in data paths

can result in small differences in LSB weight between active,

reactive, and apparent energy registers. These measurements are

internally compensated so the scaling is nearly one to one. The

relationship between these registers is shown in Table 47.

Table 47. Energy Registers Scaling

Line Frequency = 50 Hz

Line Frequency = 60 Hz

Integrator

VAR = 0.9952 × WATT

VAR = 0.9949 × WATT

Off

VA = 0.9978 × WATT

VA = 1.0015 × WATT

Off

VAR = 0.9997 × WATT

VAR = 0.9999 × WATT

VA = 0.9977 × WATT

VA = 1.0015 × WATT

ENERGY MEASUREMENT INTERRUPTS

The energy measurement part of the ADE5166/ADE5169/

ADE5566/ADE5569 has its own interrupt vector for the 8052

core, Vector Address 0x004B (see the Interrupt Vectors section).

The bits set in the Interrupt Enable 1 SFR (MIRQENL, 0xD9),

Interrupt Enable 2 SFR (MIRQENM, 0xDA), and Interrupt

Enable 3 SFR (MIRQENH, 0xDB) enable the energy measure-

ment interrupts that are allowed to interrupt the 8052 core.

If an event is not enabled, it cannot create a system interrupt.

The ADE interrupt stays active until the status bit that has created

the interrupt is cleared. The status bit is cleared when a zero is

written to this register bit.

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