AT89C51CC03U-RDTIM datasheet(86/183 Pages) ATMEL

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AT89C51CC03

4182B–CAN–09/03

CAN Controller

The CAN Controller provides all the features required to implement the serial communi-

cation protocol CAN as defined by BOSCH GmbH. The CAN specification as referred to

by ISO/11898 (2.0A and 2.0B) for high speed and ISO/11519-2 for low speed. The CAN

Controller is able to handle all types of frames (Data, Remote, Error and Overload) and

achieves a bitrate of 1-Mbit/sec at 8 MHz1 Crystal frequency in X2 mode.

Note:

1. At BRP = 1 sampling point will be fixed.

CAN Controller

Description

The CAN Controller accesses are made through SFR.

Several operations are possible by SFR:

•

arithmetic and logic operations, transfers and program control (SFR is accessible by

direct addressing).

•

15 independent message objects are implemented, a pagination system manages

their accesses.

Any message object can be programmed in a reception buffer block (even non-consec-

utive buffers). For the reception of defined messages one or several receiver message

objects can be masked without participating in the buffer feature. An IT is generated

when the buffer is full. The frames following the buffer-full interrupt will not be taken into

account until at least one of the buffer message objects is re-enabled in reception.

Higher priority of a message object for reception or transmission is given to the lower

message object number.

The programmable 16-bit Timer (CANTIMER) is used to stamp each received and sent

message in the CANSTMP register. This timer starts counting as soon as the CAN con-

troller is enabled by the ENA bit in the CANGCON register.

The Time Trigger Communication (TTC) protocol is supported by the AT89C51CC03.

Figure 43. CAN Controller Block Diagram

Bit

Stuffing /Destuffing

Cyclic

Redundancy Check

Receive

Transmit

Error

Counter

Rec/Tec

Bit

Timing

Logic

Page

DPR(Mailbox + Registers)

Priority

Encoder

µC-Core Interface

Core

Control

Interface

Bus

TxDC

RxDC

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