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AT89C51CC03U-RDTIM 数据表(PDF) 47 Page - ATMEL Corporation |
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AT89C51CC03U-RDTIM 数据表(HTML) 47 Page - ATMEL Corporation |
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47 / 183 page  47 AT89C51CC03 4182B–CAN–09/03 Overview of FM0 Operations Flash Registers (SFR) The CPU interfaces to the flash memory through the FCON register, AUXR1 register and FSTA register. These registers are used to map the column latches, HSB, extra row and EEDATA in the working data or code space. FCON Register Table 13. FCON Register FCON Register (S:D1h) Flash Control Register Reset Value= 0000 0000b 7654 3210 FPL3 FPL2 FPL1 FPL0 FPS FMOD1 FMOD0 FBUSY Bit Number Bit Mnemonic Description 7-4 FPL3:0 Programming Launch Command Bits Write 5Xh followed by AXh to launch the programming according to FMOD1:0. (see Table 16.) 3FPS Flash Map Program Space When this bit is set: The MOVX @DPTR, A instruction writes in the columns latches space When this bit is set: The MOVX @DPTR, A instruction writes in the regular XDATA memory space 2-1 FMOD1:0 Flash Mode See Table 16. 0FBUSY Flash Busy Set by hardware when programming is in progress. Clear by hardware when programming is done. Can not be changed by software. |
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