AT89C5132-ROTIL datasheet(60/182 Pages) ATMEL

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4173E–USB–09/07

AT89C5132

14. Audio Output Interface

The AT89C5132 implement an audio output interface allowing the audio bitstream to be output

in various formats. It is compatible with right and left justification PCM and I2S formats and

thanks to the on-chip PLL (see Section “Clock Controller”, page 12) allows connection of almost

all of the commercial audio DAC families available on the market.

14.1

Description

The C51 core interfaces to the audio interface through five special function registers: AUDCON0

and AUDCON1, the Audio Control registers (see Table 51 and Table 52); AUDSTA, the Audio

Status register (see Table 53); AUDDAT, the Audio Data register (see Table 54); and AUDCLK,

the Audio Clock Divider register (see Table 55).

Figure 14-1 shows the audio interface block diagram, blocks are detailed in the following

sections.

Figure 14-1. Audio Interface Block Diagram

14.2

Clock Generator

The audio interface clock is generated by division of the PLL clock. The division factor is given

by AUCD4:0 bits in AUDCLK register. Figure 14-2 shows the audio interface clock generator

and its calculation formula. The audio interface clock frequency depends on the audio DAC

used.

AUD

CLOCK

UDRN

AUDSTA.6

DSIZ

AUDCON0.1

DSEL

Clock Generator

DCLK

DOUT

SCLK

JUST4:0

AUDCON0.7:3

POL

AUDCON0.2

AUDEN

AUDCON1.0

HLR

AUDCON0.0

Data Converter

Audio Data

From C51

DUP1:0

AUDCON1.2:1

SREQ

AUDSTA.7

Audio Buffer

AUBUSY

AUDSTA.5

Data Ready

AUDDAT

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