M41T81S

Operation

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WRITE mode

In this mode the master transmitter transmits to the M41T81S slave receiver. Bus protocol is

shown in Figure 10 on page 13. Following the START condition and slave address, a logic '0'

(R/W=0) is placed on the bus and indicates to the addressed device that word address “An”

will follow and is to be written to the on-chip address pointer. The data word to be written to

the memory is strobed in next and the internal address pointer is incremented to the next

address location on the reception of an acknowledge clock. The M41T81S slave receiver

will send an acknowledge clock to the master transmitter after it has received the slave

address see Figure 7 on page 12 and again after it has received the word address and each

data byte.

Data retention mode

WRITE Cycles. Should the supply voltage decay, the power input will be switched from the

At this time the clock registers will be maintained by the attached battery supply. On power-

For a further, more detailed review of lifetime calculations, please see Application Note

AN1012.

Figure 10.

WRITE mode sequence

AI00591

BUS ACTIVITY:

S

P

SDA LINE

BUS ACTIVITY:

MASTER

DATA n

DATA n+1

DATA n+X

WORD

ADDRESS (An)

SLAVE

ADDRESS