STCD1020 datasheet(17/40 Pages) STMICROELECTRONICS

17 / 40 page

STCD1020, STCD1030, STCD1040

DC and AC parameters

17/40

IACT

Active current(5)

1 channel enabled

1.8

2 channels enabled

2.3

3 channels enabled

2.85

4 channels enabled

3.4

ISB

Standby current

All buffers disabled

μA

RIN

Input resistance

At DC level

>100

CIN

Input capacitance

f = 26 MHz

tr/f

Rise/fall times(6)

Vin = 1Vpp, CL = 10 pF

Square wave input/output

Signal bandwidth(3)

Vin =1 Vpp, -1dB, CL = 10 pF

Sine wave input/output

MHz

VENH

Enable voltage high(7)

EN1~EN4

1.2

VENL

Enable voltage low(7)

EN1~EN4

0.6

Additive phase noise(3)(8)

at 1 kHz offset

-135

dBc/

at 10 kHz offset

-145

at 100 kHz offset

-150

tRECB

Buffer recovery time from off to on

STCD10x0 active

μs

tRECC

STCD10x0 active recovery time

from standby to active

μs

Capacitive load for each channel

Resistive load for each channel

Valid for ambient operating temperature: TA = -40°C to 85°C; VCC = 2.5 V to 3.6 V; typical TA = 25°C;

Load capacitance = 10 pF (except where noted).

Clock input voltage level should not exceed supply rails.

Simulated and determined via design and NOT 100% tested.

The quiescent current is measured when the enable pins are active, but without input master clock signal (fMCLK = 0 Hz).

The active current is dependent on the master clock input Vpp and frequency and the capacitive load condition. The typical

test condition is 26 MHz sine wave with 1 Vpp master clock input, CL = 10 pF.

The rise time is measured when clock edge transfers from 10% VCC to 90% VCC. The fall time is measured when clock

edge transfers from 90% VCC to 10% VCC.

Other test results are under test condition VENH = 1.8 V and VENL = 0 V.

Guaranteed with the supply noise of 30

μ Vrms from 300 Hz to 50 kHz.

Table 9.

DC and AC characteristics (2.8 V supply) (continued)

Symbol

Parameter

Condition(1)

Min

Typ

Max

Unit

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