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STCD1020 数据表(PDF) 20 Page - STMicroelectronics |
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STCD1020 数据表(HTML) 20 Page - STMicroelectronics |
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20 / 40 page ![]() Typical operating characteristics STCD1020, STCD1030, STCD1040 20/40 Figure 15. Active current (IACT) vs. master clock input voltage level (Vpp) (STCD1040, 2.8 V version, EN1=EN2=EN3=EN4=1, 26 MHz sine wave master clock input) Figure 16. Active current (IACT) vs. input frequency (STCD1040, 2.8 V version, EN1=EN2=EN3=EN4=1, master clock input Vpp = 1 V) Active current vs. Master clock voltage level 0 1 2 3 4 5 6 Master clock voltage level Vpp(V) 10pF 20pF 30pF Active current vs. Input frequency 0 2 4 6 8 10 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 Frequency (MHZ) 10pF 20pF 30pF |
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