ST8024 datasheet(13/31 Pages) STMICROELECTRONICS

13 / 31 page

ST8024

Electrical characteristics

13/31

Table 15.

Clock output to card reader (pin CLK) (VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless

otherwise noted. Typical values are to TA = 25 °C)

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

VO(inactive)

Output voltage in inactive mode

IO(inactive) = 1 mA

0.3

No Load

0.1

IO(inactive)

Output current

CLK Inactive mode; pin

grounded

0-1

VOL

Low level output voltage

IOL = 200 µA

0.3

IOL = 70 mA (current

limit)

VCC-0.4

VCC

VOH

High level output voltage

IOH = -200 µA

0.9VCC

VCC

IOH = -70 mA (current

limit)

00.4

tR, tF

Rise and fall time

CL = 30 pF (Note 4)16

Duty factor (except for fXTALS)CL = 30 pF (Note 4)45

Slew rate

Slew up or down;

CL = 30 pF

0.2

V/ns

Table 16.

Control inputs (pins CLKDIV1, CLKDIV2, CMDVCC, RSTIN and 5 V / 3 V

(VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted. Typical values are to TA

= 25 °C) (Note 5)

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

VIL

Input voltage low

-0.3

0.3VDD

VIH

Input voltage high

0.7VDD

VDD

|ILIH|

Input leakage current high

VIH = VDD

1µA

|ILIL|

Input leakage current low

VIL = 0

µA

Table 17.

Card presence inputs (pins PRES and PRES)

(VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted. Typical values are to TA

= 25 °C) (Note 6)

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

VIL

Input voltage low

-0.3

0.3 VDD

VIH

Input voltage high

0.7 VDD

VDD+0.3

|ILIH|

Input leakage current high

VIH = VDD

5µA

|ILIL|

Input leakage current low

VIL = 0

µA

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