ST8024 datasheet(14/31 Pages) STMICROELECTRONICS

14 / 31 page

Electrical characteristics

ST8024

14/31

Note:

All parameters remain within limits but are tested only statistically for the temperature

range. When a parameter is specified as a function of VDD or VCC it means their actual value

at the moment of measurement.

To meet these specifications, pin VCC should be decoupled to CGND using two ceramic

multilayer capacitors of low ESR both with values of 100 nF and 100 nF (see Figure 10).

Permitted capacitor values are 100 + 100 nF, or 220 nF.

Transition time and duty factor definitions are shown in Figure 3;

δ = t1/(t1+ t2).

Pin CMDVCC is active LOW; pin RSTIN is active HIGH; for CLKDIV1 and CLKDIV2

functions see Table 20

Pin PRES is active LOW; pin PRES is active HIGH see Figure 8 and Figure 9; PRES has an

integrated 1.25 µA current source to GND. (PRES to VDD); the card is considered present if

at least one of the inputs PRES or PRES is active.

Table 18.

Interrupt output (pin OFF NMOS drain with integrated 20 k

Ω pull-up resistor to VDD);

(VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted. Typical values are to TA =

25 °C)

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

VOL

Low level output voltage

IOL = 2 mA

0.3

VOH

High level output voltage

IOH = -15 µA

0.75 VDD

RPU

Integrated pull-up resistor

20k

Ω Pull-up resistor to VDD

Table 19.

Protection and limitation (VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise

noted. Typical values are to TA = 25 °C)

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

|ICC(SD)|

Shutdown and limitation current pin

VCC

120

II/O(lim)

limitation current pins I/O, AUX1

and AUX2

-15

ICLK(lim) limitation current pin CLK

-70

IRST(lim) limitation current pin RST

-20

TSD

Shut down temperature

150

°C

Table 20.

Timing (VDD = 3.3 V, VDDP = 5 V, fXTAL = 10 MHz, unless otherwise noted. Typical values

are to TA = 25 °C)

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

tACT

Activation time

(See Figure 5)

180

220

µs

tDE

Deactivation time

(See Figure 7)

100

µs

Start of the windows for sending

CLK to card

(See Figure 6)

130

µs

End of the windows for sending

CLK to card

(See Figure 6)

140

µs

tdebounce

Debounce time pins PRES and

PRES

(See Figure 8)

140

µs

ST8024 数据表(PDF) 14 Page - STMicroelectronics

ST8024 数据表(HTML) 14 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

数据表下载

链接网址

ST8024 数据表(PDF) 14 Page - STMicroelectronics

ST8024 数据表(HTML) 14 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

数据表 下载

链接网址

数据表下载