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STLC5412 数据表(PDF) 63 Page - STMicroelectronics |
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STLC5412 数据表(HTML) 63 Page - STMicroelectronics |
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63 / 74 page  TIMING CHARACTERISTICS Symbol Parameter Test Condition Min. Typ. Max. Unit MASTER CLOCK FMCLK Frequency of MCLK Tolerance Including Temperature, Aging, Etc... –100 15.36 +100 MHz ppm MCLK/XTAL Input Clock Jitter External Clock Source 50 ns pk-pk tWMH Clock Pulse Width, MCLK High Level VIH =VCC – 0.5V VIL = 0.5V 20 ns tWML Clock Pulse Width, MCLK Low Level 20 ns tRM tFM Rise Time of MCLK Fall Time of MCLK Used as a Logic Input 10 10 ns ns DIGITAL INTERFACE FBCLK Frequency of BCLK Formats 1, 2 and 3 Format 4 and GCI Mode 256 512 4095 6144 KHz KHz tWBH Clock Pulse Width, BCLK High Level Measured from VIH to VIH 30 ns tWBL Clock Pulse Width, BCLK Low Level Measured from VIL to VIL 30 ns tRB Risae Time of BCLK Measured from VIL to VIH 15 ns tFB Fall Time of BCLK Measured from VIH to VIL 15 ns tSFB Setup Time, FS High or Low to BCLK Low DSI or GCI Slave Mode only 30 ns tHBF Hold Time, BCLK Low to FS High or Low DSI or GCI Slave Mode only 20 ns tDBF Delay Time, BCLK High to FS High or Low DSI or GCI Master Mode only –20 20 ns tDBD Delay Time, BCLK High to Data Valid Load = 150pF + 2 LSTTLLoads 80 ns tDBDZ Delay Time, BCLK High to Data HZ 50 ns tDFD Delay Time, FS High to Data Valid Load = 150pF + 2 LSTTLLoads 80 ns tSDB Setup Time, Data Valid to BCLK Low 0 ns tHBD Hold time, BCLK to Data Invalid 20 ns tDBT Delay Time, BCLK High to TSR Low Load = 100pF + 2 LSTTLLoads 80 ns tDBTZ Delay Time, BCLK Low to TSR HZ 50 ns tDFT Delay Tie, FS High to TSR Low Load = 100pF + 2 LSTTLLoads 80 ns D PORT IN CONTINUOUS MODE: 16KBITS/SEC tSDD Setup Time, DCLK Low to DX High or Low 50 ns tHDD Hold Time, DCLK Low to DX High or Low 50 ns tDDD Delay Time, DCLK High to DR High or Low Load = 50pF + 2 LSTTL Loads 80 ns MICROWIRE CONTROL INTERFACE FCCLK Frequency of CCLK 5 MHz tWCH Clock Pulse Width, CCLK High Level Measured from VIH to VIH 85 ns tWCL Clock Pulse Width, CCLK Low Level Measured from VIL to VIL 85 ns tRC Rise Time of CCLK Measured from VIL to VIH 15 ns tFC Fall Time of CCLK Measured from VIH to VIL 15 ns tSSC Setup Time, CSB Low to CCLK High 60 ns tHCS Hold Time, CCLK Low to CSB High 10 ns tWSH Duration of CSB High 200 ns tSIC Setup Time, CI Valid to CCLK High 25 ns tHCI Hold Time, CCLK High to CI Invalid 25 ns tDSO Delay Time, CSB Low to CO Valid Out First Bit on CO 50 ns tDCO Delay Time CCLK Low to CO Valid Load = 50 pF + 2LSTTL Loads 50 ns tDCOZ Delay Time, CCLK Low to CO HZ 50 ns tDCI Delay Time, CCLK Low to INTB Low or HZ Load = 80pF + 2LSTTL Loads 150 ns STLC5412 63/74 |
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