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STLC5412 数据表(PDF) 21 Page - STMicroelectronics |
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STLC5412 数据表(HTML) 21 Page - STMicroelectronics |
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21 / 74 page ![]() Data is transmitted in both directions at half the data clock rate. The information is clocked by the transmitter on the front edge of the data clock and can be accepted by the receiver after 1 to 1.5 pe- riod of the data clock. The data clock (BCLK) is a square wave signal at twice the data transmission frequency on Bx and Br with a 1 to 1 duty cycle. The frequency can be choosen from 512 to 6176 kHz with 16 kHz modularity. Data transmission rate depends only on the data clock rate. The Frame Clock FSa is a 8 kHz signal for syn- chronization of data transmission. The front edge of this signal gives the time reference of the first bit in the first GCI input and output channel, and reset the slot counter at the start of each frame. When some GCI channels are not selected on devices connected to the same GCI link, these time slots are free for alternative uses. GCI configuration selection is done by biasing of input pins MW, M0, CONF1, CONF2 according to Table 1. Table 1: GCI Configuration selection. Pin Number Pin name Configuration PLCC44 DIP28 LT/NT12 (1) NT/TE NT1-AUTO LT-RR-AUTO NT-RR-AUTO 43 28 MW 0000 0 42 27 M0 0111 1 27 19 S1/CONF1 S1 0 1 1 0 25 17 S2/CONF2 S2 1 1 0 0 10 7 S0/FSb/TEST2 S0 FSb TEST2 TEST2 TEST2 26 18 IO1/ES1 (2) IO1 IO1 ES1 PLDD ES1 24 16 IO2/ES2 (2) IO2 IO2 ES2 EC ES2 23 15 IO3/EC (2) IO3 IO3 EC LFS LFS 22 14 IO4/TEST1 (2) IO4 IO4 TEST1 TEST1 TEST1 35 22 SFSx/RFS (2) SFSx SFSx SFSx RFS RFS (1) Differentation between LT and NT configuration done by bit NTS in CR2 register; GCI in slave mode. When NT1-AUTO or NT-RR-AUTO configuration is selected, BCLK bit clock frequency of 512 kHz is automatically selected When NT configuration is selected, BCLK bit clock frequency of 1536 kHz is automatically selected. (2) Connected to VCC through internal pull-up resistors. STLC5412 21/74 |
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