ST6208LD1SLASHOTP datasheet(27/104 Pages) STMICROELECTRONICS

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ST6208C/ST6209C/ST6210C/ST6220C

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5.4 INTERRUPTS

The ST6 core may be interrupted by four maska-

ble interrupt sources, in addition to a Non Maska-

ble Interrupt (NMI) source. The interrupt process-

ing flowchart is shown in Figure 18.

Maskable interrupts must be enabled by setting

the GEN bit in the IOR register. However, even if

they are disabled (GEN bit = 0), interrupt events

are latched and may be processed as soon as the

GEN bit is set.

Each source is associated with a specific Interrupt

Vector, located in Program space (see Table 8). In

the vector location, the user must write a Jump in-

struction to the associated interrupt service rou-

tine.

When an interrupt source generates an interrupt

request, the PC register is loaded with the address

of the interrupt vector, which then causes a Jump

to the relevant interrupt service routine, thus serv-

icing the interrupt.

Interrupt are triggered by events either on external

pins, or from the on-chip peripherals. Several

events can be ORed on the same interrupt vector.

On-chip peripherals have flag registers to deter-

mine which event triggered the interrupt.

Figure 17. Interrupts Block Diagram

NMI

ESB BIT

VDD

LATCH

CLEARED BY H/W

AT START OF VECTOR #0 ROUTINE

VECTOR #0

LES BIT

LATCH

CLEARED BY H/W

AT START OF

VECTOR #1

VECTOR #2

VECTOR #3

VECTOR #4

LATCH

CLEARED

BY H/W AT START OF

VECTOR #2 ROUTINE

I/O PORT REGISTER

CONFIGURATION

“INPUT WITH INTERRUPT”

I/O PORT REGISTER

CONFIGURATION

“INPUT WITH INTERRUPT”

EXIT FROM

STOP/WAIT

VECTOR #1 ROUTINE

TIMER

A/D CONVERTER *

TMZ BIT

ETI BIT

EAI BIT

EOC BIT

GEN BIT

PB0...PB7

PA0...PA3

(TSCR REGISTER)

(ADCR REGISTER)

(IOR REGISTER)

* Depending on device. See device summary on page 1.

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