STLVD111

4/12

specified (Note 1, 2)

NOTE 1: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground

unless otherwise specified.

(Note 4)

otherwise specified (Figure 4)

Symbol

Parameter

Test Conditions

Value

Unit

Min.

Typ.

Max.

Output Reference Voltage

1.15

1.25

1.35

V

Power Supply Current

All driver enabled and loaded

125

160

mA

Input Capacitance

5pF

Output Capacitance

5

pF

Logic Input High Threshold

2

V

Logic Input Low Threshold

0.8

V

Logic Input Current

±10

µA

Symbol

Parameter

Test Conditions

Value

Unit

Min.

Typ.

Max.

220

300

ps

(Fig. 5, 6)

2

2.5

ns

Maximum Input Frequency

700

900

MHz

Bank Skew

(Fig. 1)

50

ps

Part to Part Skew

(Fig. 2)

100

Pulse Skew

(Fig. 3)

50

Symbol

Parameter

Test Conditions

Value

Unit

Min.

Typ.

Max.

Maximum Frequency of Shift

Register

(Fig. 7)

100

150

MHz

Clock to SI Setup Time

(Fig. 7)

2

ns

Clock to SI Hold Time

(Fig. 7)

1.5

ns

Enable to Clock Removal Time

(Fig. 7)

1.5

ns

Minimum Clock Pulse Width

(Fig. 7)

3

ns