STLVD111 datasheet(5/12 Pages) STMICROELECTRONICS

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STLVD111

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SPECIFICATION OF CONTROL REGISTER

The STLVD111 is provided with a 11 bit shift register with a Serial In and a Control Register. The purpose

is to enable or power of each output clock channel and to select the clock input. The STLVD111 provides

two working modality:

PROGRAMMED MODE (EN=1)

The shift register have a serial input to load the working configuration. Once the configuration is loaded

with 11 clock pulse, another clock pulse load the configuration into the control register. The first bit on the

serial input line enables the outputs Q9 and Q9, the second bit enables the outputs Q8 and Q8 and so on.

The last bit is the clock selection bit. To restart the configuration of the shift register a reset of the state

machine must be done with a clock pulse on CK and the EN set to Low. The control register shift register

can be configured on time after each reset.

STANDARD MODE (EN=0)

In Standard Mode the STLVD111 isn’t programmable, all the clock outputs are enabled. The LVDS clock

input is selected from Clock 0 or Clock 1 with the SI pin as shown in the Truth Table below.

TRUTH TABLE OF STATE MACHINE INPUTS

SERIAL INPUT SEQUENCE

TRUTH TABLE OF THE CONTROL REGISTER

TRUTH TABLE

OUTPUT

All Output Enabled, Clock 0 selected, Control Register disabled

All Output Enabled, Clock 1 selected, Control Register disabled

First stage stores "L", other stages store the data of previous stage

First stage stores "H", other stages store the data of previous stage

Reset of the state machine, Shift register and Control Register

BIT#10

BIT#9

BIT#8

BIT#7

BIT#6

BIT#5

BIT#4

BIT#3

BIT#2

BIT#1

BIT#0

CLK_SEL

BIT#10

BIT#(0-9)

Qn(0-9)

Clock 0

Clock 1

Qn Output Disabled

CLK 0

CLK 1

Q (0-9)

Q(0-9)

Open

XLH

Open

All drivers enable

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