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STLVD112 数据表(PDF) 6 Page - STMicroelectronics |
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STLVD112 数据表(HTML) 6 Page - STMicroelectronics |
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6 / 11 page ![]() STLVD112 6/11 LVDS SWITCHING TIMING CHARACTERISTICS (Over recommended operating conditions, unless otherwise noted. All typical values are at TA=25°C and VS1,VS2 =3.3V) AC LVTTL IN LVTTL OUT (Over recommended operating conditions, unless otherwise noted. All typical values are at TA=25°C and VS1,VS2 =3.3V) AC CONTROL OUTPUT (LOSsp, LOSch) (Over recommended operating conditions, unless otherwise noted. All typical values are at TA=25°C and VS1,VS2 =3.3V) AC LVTTL IN LVDS OUT (Over recommended operating conditions, unless otherwise noted. All typical values are at TA=25°C and VS1,VS2 =3.3V) Symbol Parameter Test Conditions Value Unit Min. Typ. Max. tW Minimum Pulse Width <1 ns Symbol Parameter Test Conditions Value Unit Min. Typ. Max. tPLH Propagation Delay Time, low-to-high- level output (50% to 50%) Measured with VIN=0 to 2.5V, fCLOCK = 1MHz, fDATA = 0.5MHz tr =tf = 0.4ns, +Duty Cycle=50% tPHL,tPLH are referred to output clock transitions. 2.4 3.9 5.6 ns tPHL Propagation Delay Time, high-to-low- level output (50% to 50%) 2.5 4.2 5.3 ns tTLH Transition Time, low-to-high-level output (10% to 90%) 0.7 1.3 1.6 ns tTHL Transition Time, high-to-low-level output (90% to 10%) 0.7 1.1 1.3 ns fopr Operative frequency 100 155 200 MHz Symbol Parameter Test Conditions Value Unit Min. Typ. Max. tPLH Propagation Delay Time, low-to-high- level output (50% to 50%) Measured with VIN=0 to 2.5V, fCLOCK = 1MHz, fDATA = 0.5MHz tr =tf = 0.4ns, +Duty Cycle=50% tPHL,tPLH are referred to output clock transitions. 2.4 3.6 4.4 ns tPHL Propagation Delay Time, high-to-low- level output (50% to 50%) 2.4 3.4 4.2 ns tTLH Transition Time, low-to-high-level output (10% to 90%) 0.9 1.9 2.3 ns tTHL Transition Time, high-to-low-level output (90% to 10%) 0.7 1.0 1.2 ns Symbol Parameter Test Conditions Value Unit Min. Typ. Max. tPLH Propagation Delay Time, low-to-high- level output (50% to 50%) Measured with VIN=0 to 2.5V, fCLOCK = 1MHz, fDATA = 0.5MHz tr =tf = 0.4ns, +Duty Cycle=50% tPHL,tPLH are referred to output clock transitions. 2.8 3.8 4.7 ns tPHL Propagation Delay Time, high-to-low- level output (50% to 50%) 2.6 3.4 4.1 ns tTLH Transition Time, low-to-high-level output (20% to 80%) 0.4 0.5 0.6 ns tTHL Transition Time, high-to-low-level output (80% to 20%) 0.4 0.6 0.7 ns fopr Operative frequency 100 155 200 MHz |
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