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December 2002

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100ps PART-TO-PART SKEW

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50ps BANK SKEW

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DIFFERENTIAL DESIGN

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MEETS LVDS SPEC. FOR DRIVER

OUTPUTS AND RECEIVER INPUTS

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REFERENCE VOLTAGE AVAILABLE

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2.625V

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HIGH SIGNALLING RATE CAPABILITY

(EXCEEDS 700MHz)

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SUPPORT OPEN, SHORT, AND

TERMINATED INPUT FAIL-SAFE (LOW

OUTPUT STATE)

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PROGRAMMABLE DRIVERS POWER OFF

CONTROL

DESCRIPTION

The STLVD210 is a low skew programmable

1-to-5 dual differential LVDS driver, designed with

clock distribution in mind. The LVDS input signals

can be either differential or single-ended if the

VBB output is used.

The STLVD210 is provided with a 11 bit shift

register with a serial in and a Control Register.

The purpose is to enable or power off each output

clock channel and to select the clock input. The

STLVD210 is specifically designed, modelled and

produced with low skew as the key goal. Optimal

design and layout serve to minimize gate to gate

skew within a device. The net result is a

dependable guaranteed low skew device.

The STLVD210 can be used for high performance

clock distribution in 2.5V systems with LVDS

levels. Designers can be take advantage of the

device’s performance to distribute low skew

clocks across the backplane or the board.

ORDERING CODES

Type

Temperature

Range

Package

Comments

STLVD210BF

-40 to 85 °C

TQFP32 (Tray)

250 parts per Tray

STLVD210BFR

-40 to 85 °C

TQFP32 (Tape & Reel)

2400 parts per reel

STLVD210

DIFFERENTIAL LVDS CLOCK DRIVER

TQFP32