STLVD210

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NOTE 1: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground

unless otherwise specified.

SPECIFICATION OF CONTROL REGISTER

The STLVD210 is provided with a 11 bit shift register with a Serial In and a Control Register. The purpose

is to enable or power of each output clock channel. The STLVD210 provides two working modality:

PROGRAMMED MODE (EN=1)

The shift register have a serial input to load the working configuration. Once the configuration is loaded

with 11-clock pulse, another clock pulse loads the configuration into the control register. The first bit on

the serial input line enables the outputs Qb4 and Qb4, the second bit enables the outputs Qb3 and Qb3

and so on. The last bit is the fewer significations. To restart the configuration of the shift register a reset

of the state machine must be done with a clock pulse on CK and the EN set to Low. The control register

can be configured on time after each reset.

STANDARD MODE (EN=0)

In Standard Mode the STLVD210 isn’t programmable, all the clock outputs are enabled.

TRUTH TABLE OF STATE MACHINE INPUTS

SERIAL INPUT SEQUENCE

Symbol

Parameter

Test Conditions

Value

Unit

Min.

Typ.

Max.

Transition Time Low to High

220

300

ps

Transition Time High to Low

220

300

ps

2

2.5

ns

Maximum Input Frequency

700

900

MHz

Bank Skew

50

ps

Part-to-Part Skew

100

Pulse Skew

60

EN

SI

CK

OUTPUT

L

X

X

All Outputs Enable

HL

First stage stores "L", other stages store the data of previous stage

HH

First stage stores "H", other stages store the data of previous stage

LX

Reset of the state machine, Shift register and Control Register

BIT#10

BIT#9

BIT#8

BIT#7

BIT#6

BIT#5

BIT#4

BIT#3

BIT#2

BIT#1

BIT#0

N.A.

Qa0

Qa1

Qa2

Qa3

Qa4

Qb0

Qb1

Qb2

Qb3

Qb4