I2C control register map

VT5376

16/30

0x61

[7:0]

IMAGE[7:0]

RO

This register contains the pixel value

when the frame dump feature has

been activated (reg 0x62, bit 0).

To read the 400 pixels from the

captured frame, the register must be

read 400 consecutive times.

0x62

[0]

Frame dump mode enable

RW

0h

If set to 1, the device will capture a

single frame. When the frame is

captured and ready to be downloaded

via reg 0x61, bit 2 (frame ready) is set.

[1]

Frame dump start

RO

0h

Bit is set at start of frame dump

[2]

Frame ready for download

0h

This bit is asserted when the captured

frame is ready to be downloaded via

reg 0x61.

When frame download is complete,

bit 3 is reset

[3]

Frame upload complete

0h

This flag is set when all 400 pixels

have been read by I2C host.

[4]

PCI Test enable

R/W

0h

If set Motion, Laser_NEN, Reset_Out

and VGate_On become PCI data

ouptuts (QCLK, FST and 2 bits serial

data)

0x82

[1]

Timer ITR enable

R/W

1h

Timer interrupt enable.

1.

Internal ACCUMULATOR is reduced from this value every time it is read.

2.

Default changes to 1 for a laser system after host_config_done (that is, system set up for optics without a lens)

Table 7.

I2C control register map (continued)

Address

Bits

Name

R/W

Default

Description