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DALC208 数据表(PDF) 4 Page - STMicroelectronics |
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DALC208 数据表(HTML) 4 Page - STMicroelectronics |
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4 / 14 page ![]() Technical information DALC208 4/14 2 Technical information 2.1 Surge protection The DALC208SC6 is particularly optimized to perform surge protection based on the rail to rail topology. The clamping voltage V CL can be calculated as follow : V CL+ = VREF2 + VF for positive surges V CL- = VREF1 - VF for negative surges with V F = VT + Rd.Ip (V F forward drop voltage) / (VT forward drop threshold voltage) According to the curve Figure 7 we assume that the value of the dynamic resistance of the clamping diode is typically R d = 0.7 Ω and V T = 1.2 V. For an IEC 61000-4-2 surge Level 4 (Contact Discharge: V g=8 kV, Rg=330 Ω), V REF2 = +5 V, V REF1 = 0 V, and if in first approximation, we assume that : Ip = Vg / Rg ′ 24 A. So, we find: –V CL+ ′ +23V –V CL- ′ -18V Note: The calculations do not take into account phenomena due to parasitic inductances. 2.2 Surge protection application example If we consider that the connections from the pin REF 2 to VCC and from REF1 to GND are done by two tracks of 10 mm long and 0.5 mm large; we assume that the parasitic inductances of these tracks are about 6 nH. So when an IEC 61000-4-2 surge occurs, due to the rise time of this spike (tr = 1 ns), the voltage V CL has an extra value equal to Lw.dI/dt. The dI/dt is calculated as: dI/dt = Ip/tr ′ 24 A/ns The overvoltage due to the parasitic inductances is: Lw.dI/dt = 6 x 24 ′ 144V By taking into account the effect of these parasitic inductances due to unsuitable layout, the clamping voltage will be : –V CL+ = +23 + 144 ′ 167V –V CL- = -18 - 144 ′ -162V We can reduce as much as possible these phenomena with simple layout optimization. It’s the reason why some recommendations have to be followed (See Section 2.3: How to ensure good ESD protection). |
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