LIS2L02AQ

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The nominal value of the capacitors, at steady state, is few pF and when an acceleration is applied the maximum

variation of the capacitive load is few hundredths of pF.

3.2 IC Interface

The complete signal processing uses a fully differential structure, while the final stage converts the differential

signal into a single-ended one to be compatible with the external world.

The first stage is a low-noise capacitive amplifier that implements a Correlated Double Sampling (CDS) at its

output to cancel the offset and the 1/f noise. The produced signal is then sent to two different S&Hs, one for

each channel, and made available to the outside.

The low noise input amplifier operates at 200 kHz while the two S&Hs operate at a sampling frequency of 66

kHz. This allows a large oversampling ratio, which leads to in-band noise reduction and to an accurate output

waveform.

All the analog parameters (output offset voltage and sensitivity) are ratiometric to the voltage supply. Increasing

or decreasing the voltage supply, the sensitivity and the offset will increase or decrease linearly. The feature

provides the cancellation of the error related to the voltage supply along an analog to digital conversion chain.

3.3 Factory calibration

The IC interface is factory calibrated to provide to the final user a device ready to operate.

The trimming values are stored inside the device by a non volatile structure. Any time the device is turned on,

the trimming parameters are downloaded into the registers to be employed during the normal operation thus

allowing the final user to utilize the device without any need for further calibration.