AAT1153

2A Step-Down Converter

PRODUCT DATASHEET

1153.2008.02.1.2

13

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The input capacitor RMS ripple current varies with the

input and output voltage and will always be less than or

equal to half of the total DC load current.

1

RMS(MAX)

2

=

To minimize stray inductance, the capacitor should be

placed as closely as possible to the IC. This keeps the

high frequency content of the input current localized,

minimizing EMI and input voltage ripple. The proper

placement of the input capacitor (C1) can be seen in the

evaluation board layout in Figures 3 and 4.

A laboratory test set-up typically consists of two long

wires running from the bench power supply to the evalu-

ation board input voltage pins. The inductance of these

wires, along with the low-ESR ceramic input capacitor,

can create a high Q network that may affect converter

performance. This problem often becomes apparent in

the form of excessive ringing in the output voltage dur-

ing load transients. Errors in the loop phase and gain

measurements can also result.

Since the inductance of a short PCB trace feeding the

input voltage is significantly lower than the power leads

from the bench power supply, most applications do not

exhibit this problem.

In applications where the input power source lead induc-

tance cannot be reduced to a level that does not affect

the converter performance, a high ESR tantalum or alu-

minum electrolytic should be placed in parallel with the

low ESR, ESL bypass ceramic. This dampens the high Q

network and stabilizes the system.

Output Capacitor Selection

The function of output capacitance is to store energy to

attempt to maintain a constant voltage. The energy is

stored in the capacitor’s electric field due to the voltage

applied.

The value of output capacitance is generally selected to

limit output voltage ripple to the level required by the

specification. Since the ripple current in the output induc-

impedance of the capacitor primarily determines the out-

put voltage ripple. The three elements of the capacitor

that contribute to its impedance (and output voltage

ripple) are equivalent series resistance (ESR), equivalent

series inductance (ESL), and capacitance (C).

The output voltage droop due to a load transient is

dominated by the capacitance of the ceramic output

capacitor. During a step increase in load current, the

ceramic output capacitor alone supplies the load current

until the loop responds. Within three switching cycles,

the loop responds and the inductor current increases to

match the load current demand. The relationship of the

output voltage droop during the three switching cycles to

the output capacitance can be estimated by:

In many practical designs, to get the required ESR, a

capacitor with much more capacitance than is needed

must be selected.

For both continuous or discontinuous inductor current

ESR

≤

ΔV

O

ΔI

L

Ripple current flowing through a capacitor’s ESR causes

power dissipation in the capacitor. This power dissipation

causes a temperature increase internal to the capacitor.

Excessive temperature can seriously shorten the expect-

ed life of a capacitor. Capacitors have ripple current rat-

ings that are dependent on ambient temperature and

should not be exceeded. The output capacitor ripple cur-

output capacitance (continuous inductor current mode

operation) is given by:

3

6

RMS

ESL can be a problem by causing ringing in the low

megahertz region but can be controlled by choosing low

ESL capacitors, limiting lead length (PCB and capacitor),

and replacing one large device with several smaller ones

connected in parallel.