LNBH23 software description

LNBH23

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7.5

Power-ON I²C interface reset

below the undervoltage lockout (UVL) threshold (6.7 V), the interface does not respond to

any I²C command and the system register (SR) is initialized to all zeroes, thus keeping the

operative and the SR can be configured by the main MCU. This is due to 500 mV of

hysteresis provided in the UVL threshold to avoid false retriggering of the power-on reset

circuit.

7.6

Address pin

It is possible to select two I²C interface addresses by means of ADDR pin. This pin is TTL

compatible and can be set as per hereafter address pin characteristics Table 10.

7.7

LNBH23 helps system designer to implement bi-directional DiSEqC 2.0 protocol by allowing

an easy PWK modulation/demodulation of the 22 kHz carrier. Between the LNBH23 and the

main MCU the PWK data is exchanged using logic levels that are compatible with both 3.3 V

and 5 V MCU. This data exchange is made through two dedicated pins, DSQIN and

DSQOUT, in order to maintain the timing relationships between the PWK data and the PWK

modulation as accurate as possible. These two pins should be directly connected to two I/O

pins of the MCU, thus leaving to the firmware the task of encoding and decoding the PWK

data in accordance to the DiSEqC protocol.

Full compliance of the system to the specification is thus not implied by the bare use of the

LNBH23. The system designer should also take in consideration the bus hardware

requirements; that can be simply accomplished by the R-L termination connected between

avoid any losses due to the R-L impedance during the tone transmission, LNBH23 has

setting the TTX function to HIGH only during the tone transmission (see DiSEqC 2.0

operation implementation in section 2.2 and 2.3). Also unidirectional DiSEqC 1.x and non-

DiSEqC systems need this termination connected through a bypass capacitor and after a R-

L filter with 15

Ω in parallel with a 220 µH-270 µH inductor but, there is no need of Tone

Decoding, thus DETIN and DSQOUT pins can be left connected to GND.

Table 7.

Register

IMON

VMON

TMON

LLC

VSEL

EN

OTF

OLF

Function

These bits are read

exactly the same as

they were left after

last write operation

(1)

(1)

0/1

These bits are set to 1 if the relative parameter

is out of the specification limits.

1.

Values are typical unless otherwise specified

2.

IMON information must be disregarded if 22 kHz TONE output is enabled

3.

VMON information must be disregarded if LLC=1 (valid only if LLC=0)