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L6722 数据表(PDF) 17 Page - STMicroelectronics

部件名 L6722
功能描述  3 Phase controller for DC/DC converters
PDF  34 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

L6722 数据表(HTML) 17 Page - STMicroelectronics

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L6722
7 Output voltage positioning
17/34
7
Output voltage positioning
Output voltage positioning is performed by programming the external resistor divider and by
correctly designing Droop Function and Offset to the reference (Optional). The output voltage is
then driven by the following relationship (See Figure 7):
Both DROOP and OFFSET function can be disabled: see Section 7.1 and Section 7.2 for
details.
L6722 embeds a Remote Sense Buffer to sense remotely the regulated voltage without any
additional external components. In this way, the output voltage programmed is regulated
between the remote buffer inputs compensating for board and connector losses. The device
senses the output voltage remotely through the pins FBR and FBG (FBR is for the regulated
voltage sense while FBG is for the ground sense) and reports this voltage internally at VSEN
pin with unity gain eliminating the errors. Keeping the FBR and FBG traces parallel and
guarded by a power plane results in common mode coupling for any picked-up noise.
When regulating output voltages higher than the reference, it is possible to insert a resistor
divider between FBR, FBG and the regulated voltage as reported in Figure 7. In this case it is
important for the external divider to have a value negligible with respect to the remote buffer
impedance that has 64k resistors.
Figure 7.
Voltage positioning
7.1
Offset and margining-mode (optional)
Positive / negative offset can be added to the programmed reference by connecting proper
network resistor between the REF_OUT and REF_IN pins. In this way is possible to manage
margining-mode by adding small offsets (positive or negative) to the regulated voltage, in order
to test the loading-circuitry in different operative conditions to check for the reliability of the
system designed.
Referring to Figure 8, a constant current (IOS=12µA) is sourced from the REF_IN pin as soon
as the device is enabled. By correctly designing ROS1 and ROS2, positive and negative offset
may be added to the reference voltage according to the status of the control signals M1 and
M2. Different operating conditions can be then considered:
V
OUT
Ref
()
R1
R2
+
R2
----------------------
=
To Vout
(Remote Sense)
Ref
FB
COMP
VSEN
64k
FBR
FBG
64k
RF
CF
RFB
REF_IN
REF_OUT
ROS
COS
R1
R2



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