L6732 datasheet(7/37 Pages) STMICROELECTRONICS

7 / 37 page

L6732

Pin connection and function

7/37

Pin connection and function

Figure 2.

Pin connection (top view)

Table 4.

Pin functions

Pin n.

Name

Function

PGOOD

This pin is an open collector output and it is pulled low if the output voltage

is not within the specified thresholds (90 %-110 %). If not used it may be left

floating. Pull-up this pin to VCCDR with a 10 k resistor to obtain a logical

signal.

SYNCH

It is a Master-Slave pin. Two or more devices can be synchronized by

simply connecting the SYNCH pins together. The device operating with the

highest FSW will be the Master. The Slave devices will operate with 180°

phase shift from the Master. The best way to synchronize devices together

is to set their FSW at the same value. If it is not used the SYNCH pin can

be left floating.

SGND

All the internal references are referred to this pin.

This pin is connected to the error amplifier inverting input. Connect it to

VOUT through the compensation network. This pin is also used to sense the

output voltage in order to manage the over voltage conditions and the

PGood signal.

COMP

This pin is connected to the error amplifier output and is used to

compensate the voltage control feedback loop.

SS/INH

The soft-start time is programmed connecting an external capacitor from

this pin and GND. The internal current generator forces a current of 10 A

through the capacitor. When the voltage at this pin is lower than 0.5 V the

device is disabled.

HTSSOP16

SGND

EAREF

PGOOD

SYNCH

COMP

VCC

LGATE

PHASE

SS/INH

PGND

VCCDR

BOOT

HGATE

OCL

OCH

L6732 数据表(PDF) 7 Page - STMicroelectronics

L6732 数据表(HTML) 7 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

数据表下载