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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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TDA7580 数据表(PDF) 20 Page - STMicroelectronics |
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TDA7580 数据表(HTML) 20 Page - STMicroelectronics |
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20 / 39 page  SAI Interface TDA7580 20/39 3 SAI Interface Figure 5. SAI Timings Note: TDSP = DSP master clock cycle time = 1/FDSP Figure 6. SAI protocol (when: RLRS=0; RREL=0; RCKP=1; RDIR=0) Table 17. SAI Timing table (Tj =-40°C to 125°C; VDD =1.7V to 1.9V, VDD3 = 3.15V to 3.45V) Cload The values on the table are consistent with a capacitance load on SAI lines of 160pF Timing Description Min Typ Max Unit tsckr Clock Cycle 302 976 ns tdt SCKR active edge to data out valid 48 65 ns tlrs LRCK setup time 25 ns tlrh LRCK hold time 25 ns tsdis SDI setup time 65 ns tsdih SDI hold time 65 ns tsckph SCK high time 146 ns tsckpl SCK low time 146 ns tsckr tsckpl tdt tsdis tlrs tsckph tlrh tsdih Valid LRCKR SDI0-1 SCKR Valid (RCKP=0) RIGHT LEFT SCKR SDI0-1 LRCKR LSB(n-1) MSB(n) MSB-1(n) MSB-2(n) |
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