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TDA7580 数据表(PDF) 22 Page - STMicroelectronics |
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TDA7580 数据表(HTML) 22 Page - STMicroelectronics |
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22 / 39 page  RDS SPI interface TDA7580 22/39 4 RDS SPI interface Figure 10. RDS SPI timings Table 18. RDS SPI timing table (Tj =-40°C to 125°C; VDD =1.7V to 1.9V, VDD3 = 3.15V to 3.45V) Cload The values on the table are consistent with a capacitance load on RDS SPI lines of 80pF Symbol Description Min Typ Max Unit Slave configured tsclk Clock cycle 1240 ns tdtr Sclk edge to MISO valid 239 365 ns tsetup MOSI setup time 255 ns thold MOSI hold time 365 ns tsclkh SCK high time width 620 ns tsclkl SCK low time width 620 ns tsssetup SS setup time 620 ns tsshold SS hold time 620 ns tssw SS pulse width 1240 ns tsclk tsclkl tdtr tsssetup tsetup tsclkh thold tsshold Valid MISO SS SCL (CPOL=0,CPHA=0) MOSI tssw |
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