ECP2 datasheet(21/386 Pages) LATTICE

21 / 386 page

2-18

Architecture

Lattice Semiconductor

LatticeECP2/M Family Data Sheet

Figure 2-18. Slice0 through Slice2 Control Selection

Edge Clock Routing

LatticeECP2/M devices have a number of high-speed edge clocks that are intended for use with the PIOs in the

implementation of high-speed interfaces. There are eight edge clocks per device: two edge clocks per edge. Differ-

ent PLL and DLL outputs are routed to the two muxes on the left and right sides of the device. In addition, the

CLKO signal (generated from the DLLDELA block) is routed to all the edge clock muxes on the left and right sides

of the device. Figure 2-19 shows the selection muxes for these clocks.

Figure 2-19. Edge Clock Mux Connections

Slice Control

Secondary Clock

Routing

Vcc

16:1

Left and Right

Edge Clocks

ECLK1

Top and Bottom

Edge Clocks

ECLK1/ ECLK2

Clock Input Pad

Routing

Input Pad

GPLL Input Pad

DLL Output CLKOP

GPLL Output CLKOP

CLKO

Left and Right

Edge Clocks

ECLK2

Routing

Input Pad

GPLL Input Pad

DLL Output CLKOS

GPLL Output CLKOS

CLKO

(Both Mux)

ECP2 数据表(PDF) 21 Page - Lattice Semiconductor

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ECP2 数据表(PDF) 21 Page - Lattice Semiconductor

ECP2 数据表(HTML) 21 Page - Lattice Semiconductor

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