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PM6670STR 数据表(PDF) 30 Page - STMicroelectronics

部件名 PM6670STR
功能描述  Complete DDR2/3 memory power supply controller
PDF  53 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

PM6670STR 数据表(HTML) 30 Page - STMicroelectronics

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Device description
PM6670S
30/53
VDDQ output voltage can be set in the range of 0.9 V to 2.6 V. Adjustable mode
automatically switches DDRSEL pin to become the power saving algorithm selector: if tied
to +5 V, the forced-PWM (fixed frequency) control is performed. If grounded or connected to
VREF pin (1.237 V reference voltage), the Pulse-Skip or Non-Audible Pulse-Skip Modes are
respectively selected.
7.1.5
Current sensing and current limit
The PM6670S switching controller uses a valley current sensing algorithm to properly
handle the current limit protection and the inductor current zero-crossing information. The
current is sensed during the conduction time of the low-side MOSFET. The current sensing
element is the on-resistance of the low-side switch. The sensing scheme is visible in
Figure 36
.
Figure 36.
Current sensing scheme
An internal 100
µA current source is connected to C
SNS pin that is also the non-inverting
input of the positive current limit comparator. When the voltage drop developed across the
sensing parameter equals the voltage drop across the programming resistor RILIM, the
controller skips subsequent cycles until the overcurrent condition is detected or the output
UV protection latches off the device (see Section 7.1.11: Over voltage and under voltage
protections on page 35
).
Table 8.
Mode-of-operation settings summary
Mode
DDRSEL
VDDQ
Operating mode
VMODE > 4.3V
VDDRSEL > 4.2V
1.8V
Pulse-Skip
1V < VDDRSEL < 3.5V
1.5V
<0.5V
VMODE < 3.7V
VDDRSEL > 4.2V
ADJ
Forced-PWM
1V < VDDRSEL < 3.5V
Non-Audible Pulse-skip
VDDRSEL < 0.5V
Pulse-Skip
HGATE
PHASE
CSNS
LGATE
PGND
PM6670
100µA·
R
ILIM
V
IN
V
OUT
I
VALLEY·RDSon
HGATE
PHASE
CSNS
LGATE
PGND
PM6670
100µA·
R
ILIM
V
IN
V
OUT
I
VALLEY·RDSon
PM6670S



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