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PM6675STR 数据表(PDF) 7 Page - STMicroelectronics |
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PM6675STR 数据表(HTML) 7 Page - STMicroelectronics |
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7 / 53 page ![]() PM6675S Electrical data 7/53 3 Electrical data 3.1 Maximum rating 19 CSNS Current sense input for the switching section. This pin must be connected through a resistor to the drain of the synchronous rectifier (RDS(ON) sensing) to set the current limit threshold. 20 PHASE Switch node connection and return path for the high side gate driver. 21 HGATE High-Side Gate Driver Output 22 BOOT Bootstrap capacitor connection. Input for the supply voltage of the high-side gate driver. 23 LIN Linear Regulator Input. Bypass to LGND by a 10µF ceramic capacitor for noise rejection enhancement. 24 LOUT LDO linear regulator output. Bypass with a 20 µF (2 x 10 µF MLCC) filter capacitor. Table 2. Pin functions (continued) N° Pin Function Table 3. Absolute maximum ratings (1) 1. Free air operating conditions unless otherwise specified. Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Symbol Parameter Value Unit VAVCC AVCC to SGND -0.3 to 6 V VVCC VCC to SGND -0.3 to 6 PGND, LGND to SGND -0.3 to 0.3 HGATE and BOOT to PHASE -0.3 to 6 HGATE and BOOT to PGND -0.3 to 44 VPHASE PHASE to SGND -0.3 to 38 LGATE to PGND -0.3 to VCC +0.3 CSNS, SPG, LEN, SWEN, LILIM, COMP, VSEL, VSNS, VOSC, VREF, NOSKIP to SGND -0.3 to VAVCC + 0.3 LPG,VREF, LOUT, LFB to SGND -0.3 to VAVCC + 0.3 LIN, LOUT, LPG, LIN to LGND -0.3 to VAVCC + 0.3 Maximum withstanding Voltage range test condition: CDF-AEC-Q100-002- “Human Body Model” acceptance criteria: “Normal Performance” ± 1250 V |
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