SPMD250STP

Phase sequence generation inside the device

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Phase sequence generation inside the device

The modules contains a three bit counter plus some combinational logic which generate

suitable phase sequences for half step, wave and normal full step drive. This 3 bit counter

generates a basic eight-step Gray code master sequence as shown

in fig. 9. To select this sequence, that corresponds to half step mode, the HALF/FULL input

(pin 4) must be kept high or unconnected.

The full step mode (normal and wave drive) are both obtained from the eight step master

sequence by skipping alternate states. This is achieved by forcing the step clock to bypass

the first stage of the 3 bit counter. The least significant bit of this counter is not affected and

therefore the generated sequence depends on the state of the counter when full step mode

is selected by forcing pin 4 (HALF/FULL) low. If full step is selected when the counter is at

any odd-numbered state, the twophase-on (normal mode) is implemented (see Figure 10).

On the contrary, if the full mode is selected when the counter is at an even-numbered state,

the one-phase-on (wave drive) is implemented (see Figure 11).

Figure 9.

The eight step master sequence corresponding to half step mode