| 数据搜索系统,热门电子元器件搜索 |
|
QST108CB1 数据表(PDF) 39 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
QST108CB1 数据表(HTML) 39 Page - STMicroelectronics |
|
39 / 51 page ![]() QST108 Electrical characteristics 39/51 6.8 RESET pin TA = -40°C to 125°C, unless otherwise specified. Table 33. RESET pin characteristics Symbol Parameter Conditions Min. Typ. Max. Unit VIL Input low level voltage VSS − 0.3 0.3x VDD V VIH Input high level voltage 0.7 x VDD VDD + 0.3 Vhys Schmitt trigger voltage hysteresis(1) 1. Data based on characterization results, not tested in production. 2V VOL Output low level voltage(2) 2. The IIO current sunk must always respect the absolute maximum rating specified in Table 22: Current characteristics on page 31 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. VDD = 5V IIO = +2mA 200 mV RON Pull-up equivalent resistor(3) 3. The RON pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin between VILmax and VDD. VIN = VSS VDD = 5V 30 50 70 k Ω VDD = 3V 90(1) tw(RSTL)out Generated reset pulse duration Internal reset sources 90(1) μs th(RSTL)in External reset pulse hold time(4) 4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on RESET pin with a duration below th(RSTL)in can be ignored. 20 μs tg(RSTL)in Filtered glitch duration 200 ns |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |