I²C bus selection

STV6412B

24/32

Note:

1

The interrupt flag will be cleared when this register is read. To prepare for a new interrupt, a

“1” must be re-written in the IT Enable bit (Reg. 04h, d7).

Table 25: Output signals (read mode)

Reg

Addr

(Hex)

Description

Bits

Data

Comments

d7

d6

d5

d4

d3

d2

d1

d0

Slow blanking TV

SCART

2

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

0

1

1

1

0

1

Input < 2 V

Input 16/9 format

Input 4/3 format

Slow blanking VCR

SCART

2

X

X

X

X

X

X

X

X

X

X

X

X

0

1

1

1

0

1

X

X

X

X

X

X

Input < 2 V

Input 16/9 format

Input 4/3 format

Interrupt flag

1

X

X

X

X

X

X

0

1

X

X

X

X

X

X

X

X

No change since read

One change has been

detected (refer to Note 1)