STV82X7 datasheet(47/156 Pages) STMICROELECTRONICS

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STV82x7

Power Supply Management

A mixed supply voltage environment requires the following voltages:

● 3.3 V capable inputs/outputs for digital pins;

● 1.8 V digital core;

● 8 V capable inputs/outputs for analog audio interfaces (capability to output 2 VRMS for SCART

requirements);

● 3.3 V for stereo ADC and DAC (analog part);

● 1.8 V for stereo ADC and DAC (digital part);

● 1.8 V for IF ADC and AGC.

These voltages will be delivered by the application with an accuracy of ±5%. For more information,

refer to Section 13.3: Power Supply Data.

Other specific DC voltages or features are provided:

● Voltage Reference and Biasing Generation (AGC, ADCs, DACs),

● Bandgap reference.

8.1

Standby Mode (Loop-through mode)

The STV82x7 provides a Loop-through mode configuration that bypasses IC functions via a SCART

I/O pin (Full Analog Path only). In this case, only a minimum power of 200 mW is required.

In Standby mode, the digital and analog power supplies are switched off, except for pins VCC_H,

VCC33_LS, VCC33_SC, and VCC_NISO which are used to maintain the SCART path with the last

configuration programmed by analog matrixing (register SCART1_2_OUTPUT_CTRL and

SCART3_OUTPUT_CTRL). When switching back to normal Full Power mode, all I²C registers are

reset except for those used in Standby mode to maintain the original configuration.

In Standby mode, the I²C bus does not operate. However, the bus can still be used by other ICs

since the I²C I/O pins (SDA and SCL) of the STV82x7 are forced into a high-impedance

configuration.

8.2

Power on Reset

The following supply voltages are involved for Power on Reset for the STV82x7:

● for 1.8 V: VDD18 on pins 38, 42, 50 and 66, VCC18_CLK1 on pin 54 and VCC18_CLK2 on pin

57.

● for 3.3 V: VDD33_IOI on pin 46 and VDD33_IO2 on pin 59.

The first condition for a valid reset is that all 1.8 V supply voltages involved have reached a minimum

valid voltage of 1.7 V and that all 3.3 V supply voltages involved have reached a minimum valid

voltage of 3.1 V. When this is the case and starting from this point, the reset must be maintained at

a low level (<1 V) for at least 100

µs then put to a high level.

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