LM3423 ONLY: FAULT TIMER AND STATUS FLAGS

Among the LM3423's additional pins are TIMR and FLT which

can be used in conjunction with an input disconnect MOSFET

switch will protect the module from various fault conditions.

An 11.5µA (typical) current is sourced from the TIMR pin

whenever any of the following conditions exist: (1) LED cur-

rent is above regulation by more than 30% (over-current

protection has engaged as described above), (2) OVLO has

engaged, or (3) thermal limit protection has engaged. An ex-

ternal capacitor on the TIMR pin acts to program the fault filter

time. When the voltage on the TIMR pin reaches 1.24V, the

device is latched off and the N-channel MOSFET open drain

FLT pin transitions to a high impedance state. The TIMR pin

will be immediately pulled to ground (reset) if the fault condi-

tion is removed at any point during the filter period.

If immediate latching is desired, simply use a 220pF timing

cap on the TIMR pin. When using the EN and OVP pins in

conjunction with the RPD pull-down pin, a race condition ex-

ists when exiting the disabled (EN low) state. When disabled,

the OVP pin is pulled up to the output voltage because the

RPD pull-down is disabled, and this will appear to be a real

OVLO condition. The timer pin will immediately rise and latch

the controller to the fault state. To protect against this behav-

ior, a minimum capacitor should be populated from the TIMR

pin to AGND of 220pF.

30067360

FIGURE 5. OVP Resistive Divider Grounded with RPD

If fault latching operation is not required, short the TIMR pin

to ground. Note that if the TIMR pin is shorted to ground, the

FLT flag function will also be disabled. When enabled, the FLT

pin can be used in conjunction with an external P-channel

MOSFET transistor to protect the module from shorts to

ground on the output, as shown in the full featured application

schematic (see Figure 15). A latched fault condition can be

cleared by pulling the EN pin low long enough for the V

to drop below 4.1V (approximately 200ms), forcing the TIMR

pin to ground, or by a complete power cycle.

The LM3423 also includes an LED Ready (LRDY) flag to no-

tify the system that the LEDs are in proper regulation. The N-

channel MOSFET open drain LRDY pin is pulled low

whenever any of the following conditions are met: (1) V

CC

UVLO has engaged, (2) LED current is below regulation by

more than 20%, (3) LED current is above regulation by more

than 30% (over-current protection has engaged), (4) over-

voltage protection has engaged, (5) thermal limit protection

has engaged, or (6) the part has been latched off because of

a persistent fault condition. Note that the LRDY pin is pulled

low during startup of the device and remains low until the LED

current is in regulation.

Application Information

PREDICTIVE OFF-TIME TOPOLOGY

A History Lesson

Any clocked peak current mode converter has a right half

plane zero when duty cycles exceed 50%, often referred to

as “current mode instability” or “sub-harmonic oscillation”. In

this context the word “clocked” should be considered to be a

free running oscillator that starts a new “on” cycle with each

tick. The right half plane zero manifests itself by a long on-

time, short off-time cycle followed by a short on-time, long off-

time cycle.

This instability leads to high stress in the components, creates

large voltage and current ripple at half of the clocked frequen-

cy, and often becomes audible. Slope compensation is usu-

ally introduced into the control system to prevent this

instability. As the required duty cycle approaches unity, the

amount of required slope compensation increases accord-

ingly. Further complicating the problem, a boost converter

requires significantly more slope compensation than its buck

counterpart, thus becoming impractical for large voltage

transformation ratios. This translates to the necessity of lim-

iting the maximum duty cycle in a boost converter and thus

the voltage transformation ratio.

History Learned is Not Repeated

The LM3421/LM3423 controllers feature a different constant

frequency control scheme, called predictive off-time control.

This topology has several innate advantages:

•

By not being clocked it has no current mode instability at

any duty cycle.

•

Allows duty cycles and thus voltage transformation ratios

that would be impractical in a clocked current mode

system, especially in a boost topology.

•

Requires no slope compensation.

The only disadvantage is that synchronization to an external

reference frequency is generally not available. Synchroniza-

tion is “clocking” just like in an internal free running oscillator

and would reintroduce the right half plane zero unless it is

done with a phase locked loop.

SETTING THE SWITCHING FREQUENCY

For the boost, buck-boost, and SEPIC configurations, an ex-

ternal resistor connected between the RCT pin and the drain

of the main switching transistor, V

capacitor C

switching frequency. To set the operational frequency (f), the

R

We recommend a value of 1nF for CT and using that value,

this simplifies the equation to:

The R

to the device.

Buck Configuration

When the device is used to implement the buck topology the

control law is different. The internal circuitry of the device is

designed to run constant frequency in a boost, buck-boost or

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