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STPC12HDYI 数据表(PDF) 82 Page - STMicroelectronics |
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STPC12HDYI 数据表(HTML) 82 Page - STMicroelectronics |
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82 / 111 page ![]() DESIGN GUIDELINES 82/111 Issue 1.0 - July 24, 2002 In the case of higher clock load it is recommended to use a zero-delay clock buffer as described in Figure 6-9. This approach is also recommended when implementing the delay on PCICLKI according to the PCI section of the Electrical Specifications chapter. Figure 6-9. PCI clock routing with zero-delay clock buffer PCICLKI PCICLKO Device A Device B Device C PLL Device D PCICLKI PCICLKO Device A Device B Device C PLL Device D CY2305 CY2305 Implementation 1 Implementation 2 |
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