STPC12HDYI datasheet(35/111 Pages) STMICROELECTRONICS

35 / 111 page

STRAP OPTION

Issue 1.0 - July 24, 2002

35/111

3.1. STRAP OPTION REGISTER DESCRIPTION

3.1.1. STRAP REGISTER 0

This register is read only.

STRAP0

Access = 0022h/0023h

Regoffset =04Ah

543210

MD[7]

MD[6]

MD[9]

MD[8]

RSV

MD[5]

MD[4]

MD[17]

This register defaults to the values sampled on the MD pins after reset

Bit Number Sampled

Mnemonic

Description

Bits 7-6

MD[7:6]

PCICLK PLL set-up: The value sampled on MD[7:6] controls the PCICLK

PLL programming according to the PCICLK frequency.

MD7 MD6

PCICLK frequency between 16 & 32 MHz

PCICLK frequency between 32 & 64 MHz

Reserved

Bits 5-4

MD[9:8]

Mode selection:

MD9 MD8

0 ISA mode: ISA enabled, PCMCIA & Local Bus disabled

1 PCMCIA mode: PCMCIA enabled, ISA & Local Bus disabled

0 Local Bus mode: Local Bus enabled, ISA & PCMCIA disabled

1 Reserved

Bit 3

Rsv

Reserved

Bit 2

MD[5]

Host Memory synchronization. This bit reflects the value sampled on

[MD5] and controls the MCLK/HCLK synchronization.

0: MCLK and HCLK not synchronized

1: MCLK and HCLK synchronized.

Bits 1-0

MD[4], MD[17]

PCICLK division: These bits reflect the values sampled on [MD4] and

MD[17] to select the PCICLK frequency.

MD4 MD17

PCI Clock output = HCLK / 4

PCI Clock output = HCLK / 3

PCI Clock output = HCLK / 2

STPC12HDYI 数据表(PDF) 35 Page - STMicroelectronics

STPC12HDYI 数据表(HTML) 35 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载