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STPCE1EDBC 数据表(PDF) 44 Page - STMicroelectronics |
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STPCE1EDBC 数据表(HTML) 44 Page - STMicroelectronics |
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44 / 87 page  ELECTRICAL SPECIFICATIONS 44/87 Release 1.3 - January 29, 2002 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 10d Memory access to 8-bit ISA Slave 2T Cycle 10e SA[19:0] & SBHE valid before IOR#, IOW# asserted 2T Cycles 11 ISACLK2X to IOW# valid 11a Memory access to 16-bit ISA Slave - 2BCLK 2T Cycles 11b Memory access to 16-bit ISA Slave - Standard 3BCLK 2T Cycles 11c Memory access to 16-bit ISA Slave - 4BCLK 2T Cycles 11d Memory access to 8-bit ISA Slave - 2BCLK 2T Cycles 11e Memory access to 8-bit ISA Slave - Standard 3BCLK 2T Cycles 12 ALE# asserted before ALE# negated 1T Cycles 13 ALE# asserted before MEMR#, MEMW# asserted 13a Memory Access to 16-bit ISA Slave 2T Cycles 13b Memory Access to 8-bit ISA Slave 2T Cycles 13 ALE# asserted before SMEMR#, SMEMW# asserted 13c Memory Access to 16-bit ISA Slave 2T Cycles 13d Memory Access to 8-bit ISA Slave 2T Cycles 13e ALE# asserted before IOR#, IOW# asserted 2T Cycles 14 ALE# asserted before AL[23:17] 14a Non compressed 15T Cycles 14b Compressed 15T Cycles 15 ALE# asserted before MEMR#, MEMW#, SMEMR#, SMEMW# negated 15a Memory Access to 16-bit ISA Slave- 4 BCLK 11T Cycles 15e Memory Access to 8-bit ISA Slave- Standard Cycle 11T Cycles 18a ALE# negated before LA[23:17] invalid (non compressed) 14T Cycles 18a ALE# negated before LA[23:17] invalid (compressed) 14T Cycles 22 MEMR#, MEMW# asserted before LA[23:17] 22a Memory access to 16-bit ISA Slave. 13T Cycles 22b Memory access to 8-bit ISA Slave. 13T Cycles 23 MEMR#, MEMW# asserted before MEMR#, MEMW# negated 23b Memory access to 16-bit ISA Slave Standard cycle 9T Cycles 23e Memory access to 8-bit ISA Slave Standard cycle 9T Cycles 23 SMEMR#, SMEMW# asserted before SMEMR#, SMEMW# negated 23h Memory access to 16-bit ISA Slave Standard cycle 9T Cycles 23l Memory access to 16-bit ISA Slave Standard cycle 9T Cycles 23 IOR#, IOW# asserted before IOR#, IOW# negated 23o Memory access to 16-bit ISA Slave Standard cycle 9T Cycles 23r Memory access to 8-bit ISA Slave Standard cycle 9T Cycles 24 MEMR#, MEMW# asserted before SA[19:0] 24b Memory access to 16-bit ISA Slave Standard cycle 10T Cycles 24d Memory access to 8-bit ISA Slave - 3BLCK 10T Cycles 24e Memory access to 8-bit ISA Slave Standard cycle 10T Cycles 24f Memory access to 8-bit ISA Slave - 7BCLK 10T Cycles 24 SMEMR#, SMEMW# asserted before SA[19:0] 24h Memory access to 16-bit ISA Slave Standard cycle 10T Cycles 24i Memory access to 16-bit ISA Slave - 4BCLK 10T Cycles 24k Memory access to 8-bit ISA Slave - 3BCLK 10T Cycles 24l Memory access to 8-bit ISA Slave Standard cycle 10T Cycles Table 4-11. ISA Bus AC Timing Name Parameter Min Max Units Note: The signal numbering refers to Table 4-7 |
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